It is well known that the construction of CMOS integrated circuits generally begins with the fabrication of a semiconductor substrate surface of two different conductivity types, usually in the form of regions of n-conductivity type adjacent regions of p-conductivity type. In one form, such a surface could be a p-type substrate having a n-well or tub region formed therein. Thus, the p-channel devices are formed in the n-well and the n-channel devices are formed in the surface that remains p-conductivity type. More recently, both n- and p-conductivity wells have been formed within the substrate, which is often lightly doped, n.sup.- conductivity type. As the dimensions of integrated circuit MOS devices have become smaller, there is an increased danger of punchthrough currents occurring, for example, between the p.sup.+ source/drain regions of the p-channel devices in the n-wells and the adjacent p-wells. Essentially, a parasitic device is formed across the interface between the n- and p-conductivity regions. This phenomenon will occur even with the field isolation region in place. The voltage necessary to turn on this parasitic device is termed the "field threshold voltage" and is assigned the symbols V.sub.TPF for n-well field threshold voltage and V.sub.TNF for p-well field threshold voltage.
A straight-forward approach for solving this problem would be to increase the doping in the wells. However, such a technique undesirably degrades the performance of the devices in the wells. The customary solution that has evolved in answer to the problem is to use a channel stop structure beneath the field isolation region to prevent the punchthrough currents from passing through the well interface. Typically, a dopant is introduced into a substrate before the formation of the isolation region, and during the formation of the isolation region, the channel stop structure is pushed into the substrate.
Shown in FIG. 1 is a semiconductor substrate 10 having a p-well 12 and n-well 14 formed by known processes. The substrate 10 is covered by a pad oxide layer 16 to protect the silicon from implant damage, and the future active device regions are covered by patterned nitride layer 18 where the exposed oxide regions between nitride regions 18 constitute the areas where the field isolation structures are to be formed. Masking the n-well 14 is photoresist mask 20 which protects n-well 14 from the boron implant schematically illustrated by the circle symbols. As shown, the nitride 18 over the p-well 12 also masks the boron implant from the future n-channel device active area. As a result, the boron channel stop implant only enters p-well 12 adjacent the interface 22 between the two wells 12 and 14.
Subsequent to the step shown in FIG. 1, the photoresist layer 20 is removed and a conventional local oxidation of silicon (LOCOS) process is performed to grow field silicon dioxide isolation regions 24 between the patterned nitride areas 18, which are subsequently removed to give the structure seen in FIG. 2. The heating step of the LOCOS process also anneals and activates the boron implanted in FIG. 1 to form a channel stop 26 beneath the central isolation region 24. Unfortunate problems with the use of boron as a dopant to form the channel stop region 26 as shown in FIG. 2 include the fact that it may migrate to an undesirable location, such as deeper than the desired position, and the fact that the boron may be absorbed by the isolation region 24. Additionally, the boron may also become diffused and less concentrated than desired in the preferred channel stop positions, as a result of one or both of these problems. It will be understood that the region 26 does not have a sharply defined boundary as might be suggested by the illustration. It is beneficial to analyze the boron distribution one dimensionally using a spreading resistance profile (SRP) for the channel stop 26, as seen in FIG. 14. Channel stop 26 of FIG. 2 is most accurately represented by the curve on the right for boron only. In this curve the boron impurity present has clearly diffused out from its position of greater concentration nearer the surface of the substrate, x=0 microns (um). The curve to the left is more illustrative of the desired dopant distribution for a channel stop structure. The peak of the boron doping 26 illustrated in FIG. 2 is lower than desired, and the resultant channel stop may undesirably permit punchthrough currents. The incorrect positioning of the channel stop 26 dopant peak concentration is more likely to occur due to subsequent processing of the semiconductor wafer as other device features are formed which require thermal cycles, which are the causes of the dopant redistribution.
Thus, it would be advantageous if the channel stop structures for adjacent CMOS wells could be improved with respect to preventing punchthrough currents but at the same time avoiding over-doping the wells.